SIM51 Web

THE 8051 WORKSPACE
A browser-first teaching debuggerPREVIEW / 1.0.0
Workspace / 01

Debugger workspace

Inspect the machine one moment at a time.

8051 architectureReal 8051 worker
connecting
STEPS—
CYCLES—
Source has changed. Apply source to load the new editor contents before running or stepping.

Address breakpoints

Break before the instruction at a hexadecimal CODE address, even for HEX without source.

    No address breakpoints.

    Screen update frequency

    Updates the display after N executed instructions. Does not change the CPU clock, machine cycles or peripheral timing.

    Current display cadence: 1 instructions

    Only editable source, line breakpoints and view preferences are saved on this device.

    Intel HEX program I/O

    Imported HEX is machine code, not assembly source. Import replaces the loaded program only after validation and never runs it automatically.

    Editable source is not the loaded machine program

    01 / SOURCE

    Source editor

    demo.asm
    ASM · 805130 lines● Modified
    ●Changes not loadedApply source to sync
    Gutter dots toggle source-line breakpoints · Ctrl / ⌘ + Enter to run or pause
    02 / HARDWARE

    Virtual board

    Keypad + digits + INT0 + sample I/O
    P1 SEGMENTS / P3 SELECT / P0.7 GATE4-DIGIT MEMORY
    D0
    D1
    D2
    D3

    Digits retain their last sample on each P0.7 low-to-high gate edge. Browser frame rate does not advance the display.

    P0 MATRIX4 × 3

    Hold a key through the CPU scan. # clears the course entry; * is a spare key.

    P3.2 / INT0ACTIVE LOW
    RELEASEDP3.2 pin —

    Hold to pull P3.2 low. Release for the normal P3 pull-up. The CPU program controls interrupt enable and service.

    LECTURE SAMPLE I/OPHYSICAL PINS · NO SFR EDITS

    Switches · P2.0–P2.3

    Toggle to pull a pin low. Off releases the drive to the P2 pull-up.

    LEDs · P1.0–P1.7

    Read-only resolved P1 pins, active low. LEDs do not drive the CPU or display.

    T0 · P3.4

    RELEASEDP3.4 pin —

    Hold to drive P3.4 low, release to high impedance. Only executed CPU instructions and core timer logic may count edges. P3.4 also senses display digit selection.

    OUTPUT MONITOR READ ONLY

    Connecting to local worker…

    UART / EXTERNAL HOST

    Serial terminal

    Completed TX only

    EdSim text sends a trailing 0Dh (CR); a HEX list such as {56, 3a, e7} sends exactly those bytes without CR. Prefix a brace list with a backslash to send it as literal text. Enter sends EdSim-formatted bytes; raw ASCII remains available for existing course exercises.

    Printable ASCII (20h–7Eh). EdSim text sends one trailing 0Dh.

    Next host bytes (text): 0D

    EdSim host baud and parity are applied after Worker acknowledgement. Host TX drives the external UART wire, MCU RXD/TXD remain fixed at P3.0/P3.1, and received bytes appear only after physical decoding. Changing host framing resets in-flight host frames. Course mode retains its legacy direct-byte compatibility path.

    RX transcript (CPU completed TX)0 completed bytes

      No completed TX frames yet.

      RX queued —SCON —RI —TI —REN —TH1 —TL1 —TR1 —
      03 / CPU STATE

      Registers

      Hex view
      PCProgram counter
      ————h
      ACCAccumulator
      ——h
      BB register
      ——h
      PSWStatus word
      ——h
      SPStack pointer
      ——h
      DPTRData pointer
      ————h
      Values come from worker snapshots○ HOLD
      TIMER 0 / MACHINE CYCLES

      Timer 0

      Read-only SFR snapshot
      TMOD
      —
      TR0
      —
      TF0
      —
      TH0
      —
      TL0
      —
      COUNT
      —
      04 / DIGITAL I/O

      Port monitor

      P0 – P3
      P0—
      ---- ----
      P1—
      ---- ----
      P2—
      ---- ----
      P3—
      ---- ----

      128 bytes of internal data RAM. Addresses and bytes are hexadecimal.

      No data for this memory range yet.

      Request a byte edit

      Write IRAM, SFR latch storage, or CODE. CODE edits may differ from source.

      Peripheral board profile

      Hardware settings storage: loading
      Real 8051 execution and physical input. P0.0–P0.3 select keypad rows, P0.4–P0.6 sense columns, and P0.7 has an explicit weak-high pull and display gate. P1 supplies active-low segments while P3.3/P3.4 select a digit. Port monitor bytes are CPU latches, not resolved input pins. The momentary INT0 drive pulls P3.2 low without writing the P3 latch. SW1–SW4 independently pull P2.0–P2.3 low, the P1 LEDs only sense resolved pins, and the momentary T0 drive pulls P3.4 low without changing timer registers. CPU instructions sample physical pins inside the worker, and read-modify-write operations preserve latch semantics.